The ability to assess the merits of proposed space-time coding techniques relies on very accurate channel models, detailed channel measurements, or prototyping testbeds. Channel modeling is attractive since simulations may be executed fairly quickly on a computer and results are reproducible. Although channel models are usually only approximate, their ease of use makes them invaluable for the initial stages of algorithmic development. Detailed channel measurements go one step beyond channel modeling, allowing the space-time coding designer to test proposed algorithms on real-world channels. Unfortunately, detailed measurements are somewhat scarce, and those that are available represent only a small fraction of possible propagation channels. Advanced multiple-antenna prototyping testbeds, on the other hand, not only allow the designer to test algorithms in many different environments, but also help assess the feasibility of algorithms for real-time implementation. Such testbeds serve as a final testing ground before dedicated system development is performed.
We have developed a preliminary MIMO prototyping testbed, employing 4 transmit and receive elements, which is scalable to 8 elements. The architecture is based on a Pentek DSP platform, allowing rapid development of algorithms in C or C++. Embedded PCs enhance the usability of system, since input/output data may be quickly manipulated in Matlab, and valuable audio/video streaming resources are easily leveraged from the operating system. The following figure depicts a block diagram of the system.
Transmit symbols for four independent data streams are generated on the embedded PC, converted into complex baseband signals, and passed via the VME bus to four separate TI TMS3206203 fixed-point DSPs. The DSPs perform pulse-shaping and pass the resulting baseband I/Q waveforms to the Pentek 6229 digital upconverter (DDC), which interpolates and upconverts to an 8~MHz IF. A custom RF chassis mixes each IF data stream with the 2.45~GHz local oscillator (LO) signal from the microwave source and feeds the resulting signal to four separate transmit antennas. After passing through the channel, these signals are intercepted by four transmit antennas, amplified, mixed down to the 8~MHz IF, amplified by four automatic gain control (AGC) blocks, and passed to the digital down converters (DDC) in another Pentek VME chassis. The DDCs perform anti-alias filtering, A/D conversion, digital downconversion to baseband, low-pass filtering, and decimation. Four TI TMS320C6203 fixed point DSPs receive the I/Q baseband streams, perform matched filtering, and pass decimated matched filter outputs to the embedded PC.
System operation requires carrier, symbol, and frame synchronization. Theoretically, this synchronization could be achieved through the software on the DSPs. However, to focus on the space-time coding aspect, synchronization is achieved by locking all carriers and sample clocks to a common 10~MHz reference. Frame and symbol time synchronization is obtained by initially transmitting a known pseudo-random code with a period equal to the frame length. By finding the optimal alignment of the known code with the received signal, symbol timing and the start of the frame are immediately apparent. For our initial tests, transmit and receive subsystems are connected via a cable carrying the 10~MHz reference. For future deployment, we intend to use GPS or Rubidium time/frequency standards for untethered operation.
We have chosen a DSP-based platform for our space-time system, combining good system performance with a fairly modest development cycle. The following figure shows a photograph of the transmit DSP chassis, populated with two Pentek 4292 DSP boards, one of which is currently used. A single 4292 DSP board has four TI TMS320C6203 200~MHz fixed point DSP processors, each of which is connected to a Pentek 6229 DUC via a high-speed FIFO. The 6229 provides interpolation, upconversion of baseband I/Q signals to a real IF waveform, and 12-bit D/A conversion at sample rates up to 200~MS/s.
The figure below also shows a photograph of the receive DSP chassis, populated with four Pentek 4292 DSP boards and a single Pentek 4292 DSP board. Currently, only two 4292 boards are used. Each 4292 board has four TI TMS320C6203 300~MHz fixed point DSP processors, two of which are connected to a Pentek 6216 DDC, and the other two are available for additional per-channel processing. The 6216 provides anti-alias filtering, 12 bit A/D conversion at sample rates up to 64~MS/s, downconversion from a real IF waveform to complex baseband, low-pass filtering, and decimation, representing a complete digital receiver front-end.
Utility of the system is enhanced by a Concurrent VP CP1/P3x embedded PC in each chassis, housing an Intel Pentium III 1~GHz processor with 256MB RAM, and providing connectivity to standard PC peripherals. The PC runs the Microsoft Windows operating system, allowing immediate data processing with Matlab and the ability to leverage audio/video multimedia support built into the operating system.
A custom RF chassis provides signal processing of the microwave carrier at transmit and receive, depicted below. Each RF chassis incorporates a broadband 0-10~GHz backplane that provides LO, power, and IF signals to each of 16 possible transmit or receive cards. These cards provide the required mixing, amplification, and filtering at the band of interest. The receive chassis also contains a custom four-channel AGC card, utilizing the AD8367 500~MHz variable gain amplifier, allowing the input signal to vary over a 60~dB range.
Two antenna types that have used with the system: patch antennas and monopole antennas. The patch antenna array consists of four half-wavelength separated, dual-polarized patch antennas, providing up to 8 possible transmit/receive feeds. The monopole antennas are built by soldering a whip to the center of a standard bulkhead connector. A 33x33 drilled grid allows a variety of custom antenna arrays to be quickly configured.
Software has initially been developed with a minimalist approach, where future effort will focus on the development of advanced algorithms that more fully utilize system resources. With this mind set, the DSP processors perform only rudimentary functions, such as matched-filtering, pulse-shaping, decimation, and initial synchronization. More complex functions, such as data multiplexing and space-time processing are performed on the embedded host PCs, and symbol rates have been scaled to a modest level to allow processing in real-time.
The first application we developed on this platform is a video streaming demonstration employing all four transmit and receive channels to effectively quadruple data throughput. To obtain a transmit video stream, we developed a simple custom Windows DirectShow filter that runs on the embedded PC at the transmitter. The filter can connect to any standard DirectShow components, allowing video frames to be obtained from AVI files, MPEG 1/2 files, Webcams, etc., without any additional development. A simple C transmit application accepts these video frames, resizes the frames according to available throughput, and interleaves pixels to generate up to four symbol streams. Symbols are converted to I/Q signal-space values, where the allowable constellations are BPSK, 4QAM, 16QAM, or 256QAM. The application generates a single frame of data consisting of a header of Walsh codes for channel estimation, followed by a payload of I/Q values of the video symbols.
The DSP platform accepts I/Q symbol data at the rate of 250~kS/s per channel. When the DSP platform is ready for data, an interrupt is issued to the embedded PC, at which point data is transferred to global shared SDRAM via the VME bus. Software on each TI DSP processor then converts its I/Q data stream in SDRAM to 8-sample pulses, which are then transferred to each DUC FIFO.
On the receiver, each DDC provides I/Q data samples to a single TI DSP, which performs matched filtering and divide-by-8 decimation and stores the resulting samples in global shared SDRAM. When a complete block of data is available, the DSP platform interrupts the embedded host PC. A simple C receive application waits for this interrupt and copies the data via the VME bus to host memory. This application estimates the channel matrix coefficients from the known training data at the beginning of each frame, performs a pseudo-inverse of the channel matrix, and multiplies the receive streams by the inverted channel to obtain estimates of the I/Q samples of each transmit stream. Based on the current constellation, a decision rule then produces estimates of the original symbols. The symbols are combined to form the original video data, which is fed to another custom DirectShow filter, allowing video frames to be displayed in real-time or dumped to a file. The following two sample video streams demonstrate operation of the system in a rich multipath environment. Here, a movie trailer in raw YUV format was sent over the channel at the rate of 15 FPS and a resolution of 180x120 pixels. The system bandwidth was fixed by setting the symbol rate at 250 kS/s, and the constellation was 16QAM. When only a single antenna is used at transmit and receive, 250 kS/s with 16QAM yields 1Mbit/s throughput, allowing only 3 bits to represent intensity (Y) and no bits for color (UV). When four antennas are used, without increasing power or bandwidth, we can transmit four times as much data (4Mbit/s), allowing 6 bits for Y and 6 bits for UV. The improvement in the video quality is obvious.
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Another simple application developed allows measurement of symbol error rate (SER) with the same space-time coding scheme. However, in this case, instead of transmitting video data, a known PN23 code is used to generate symbols in each frame payload. After decoding the symbols, the receiver immediately computes the SER. We can see how sensitive the SER of the algorithm is to the conditioning of the channel matrix by storing the singular values of the estimated channel in each frame. The figure below plots the average SER of the 4-element space-time processing scheme when the transmitter and receiver are in our laboratory. Here, two dual polarization patches were used at transmit and receive, and the directional elements were pointed away from each other. The transmitter was fixed and the receiver assumed several points along a prescribed path. The plot also plots the singular values of the channel, demonstrating that the algorithm only has low SER when all singular values are fairly large.
We have presented a real-time DSP-based testbed capable of implementing fairly advanced space-time MIMO architectures. Utility of the system was demonstrated by describing a real-time video application and showing SER performance of a simple space-time decoding scheme. In the future, we intend to write software for more advanced space-time algorithms to fully utilize the resources of the platform. Such effort will demonstrate real-world performance of existing algorithms and will allow a feasibility assessment of these proposed algorithms.