Class Schedule

Date

Description

14 Jan 2004

Milestone 1: Differential Encoding
Each group has 5 minutes to present their proposal for the differential encoding standard. At the end of the 5 presentations, we will have a short discussion and vote. If there is no majority, Professors Rice and Jeffs will make the final decision.

21 Jan 2004

Fundamentals of RF Design
Special presentation on RF front-end design by Professor Michael Jensen.

4 Feb 2004

Formal Design Review
This is a 15 minute presentation where you provide a detailed review of your design. Information should include:

Complete RF front-end design. At a minimum you should demonstrate:

Filter specifications

Analysis of adjacent channel interference, noise, and image rejection levels

Knowledge of the external RF environment

Hardware parts list

Detailed block diagram, schematic, and chassis layout.

A Working Matlab Code Demonstration

Demonstrate operation on provided data file.

DSP loading estimate including count of the number of multiples and adds per second, estimate of the required level of optimization on the DSP processor (amount of parallelization).

Identify (in code) data debug test points and what signals should look like (debug tools).

18 Feb 2004

Milestone 3: Software Demonstrations
DSP Matched Filter Demonstration

Connect the I-Q Baseband outputs of the ESG-D Signal Generator to the A/D converter inputs on the TI EVM.

Direct the digital matched filter outputs to the D/A converters on the on the TI EVM.

Connect the TI EVM D/A converter outputs to the digital oscilloscope for display.

The synchronizer loops do not need to be working. But include a fixed phase rotation in your DSP code as a place holder for the carrier phase synchronization PLL.

25 Feb 2004

Milestone 4: RF Hardware Demonstration
Progress report and interim demonstration of the RF front-end design. You must demonstrate a fully functioning RF front-end or provide convincing evidence that the RF front-end will be completed by the Milestone 6 date.

3 Mar 2004

Milestone 5: DSP Code Demonstration

Connect the I-Q Baseband outputs of the ESG-D Signal Generator to the A/D converter inputs on the TI EVM.

Direct the digital matched filter outputs to the D/A converters on the on the TI EVM.

Connect the TI EVM D/A converter outputs to the digital oscilloscope for display.

The AGC and carrier phase synchronization PLL should be working. Design a test to demonstrate that the carrier phase PLL locks and that the AGC is working properly.

31 Mar 2004

Milestone 6: Fully Integrated System Demonstration

All DSP functions, including symbol timing recovery should be functioning. Output the downsampled and interpolated matched filter outputs through the TI EVM D/A converters to the digital oscilloscope. What should we see?

Demonstrate a fully integrated system: Antenna, RF front-end, and baseband DSP subsystem.

Although not required for this milestone, you should make sure your system can communicate with the bit error rate tester.

5 Apr 2004

Final Report, due 5:00 PM

9 Apr 2004

Senior Project Competitions

All senior project competitions will be held in conjunction with Industry Day. The competition will be in the morning in the Garden Court in the Wilkenson Center (ELWC). Lunch will be provided at 12:00 noon in Room 3224 ELWC.

Final Oral presentations will be made to the judges (external engineers from industry). This will probably be in the afternoon. Exact time and location to be announced...