The Xilinx Design System is the tool we will use to write our VHDL code and/or to draw our schematics and simulate them electronically. If we draw a schematic, the schematic program will generate a VHDL program that includes all the information in our schematic.

 

In order to use our Xilinx software and Xilinx FPGA chip, all of our designs must be made with parts that Xilinx Design Manager recognizes. These parts are the parts which are included in the Xilinx library. This library is included with the Xilinx WebPACK tool. A screen shot of the project manager is shown below in Figure 1.

 

Figure 1: The Xilinx Design System

Building a Circuit

To build a schematic in Xilinx:
 

• Open a new project by selecting New Project... from the File menu. This will pop up the window shown in Figure 3.
   

Figure 3: New Project

• Give your project a name and location. Make sure the Device Family is Virtex2, the Device is xc2v40, the Package is cs144, and the Speed Grade is -5. Make sure the Design Flow is XST VHDL. Then click OK.
   
• Now we can create a schematic for our design. In Xilinx our designs are called sources, so we must first create a new source. To do this, select New Source... from the Project menu. The New Source dialog box then appears. Click Schematic and then give your source a name. Click Next and then Finish. A new schematic window will open.
  If we want to write a new VHDL file, we would select VHDL module instead of schematic.

 

• As stated in the Overview page, Xilinx can be used to design many different types of circuits. You can place the Xilinx parts for your design by selecting the part you want from the symbol browser menu to the right of your schematic (shown in Figure 5). If a symbol browser is not opened, open it by clicking the "Add symbol" icon.

 

• In this browser you may either view all of the parts at once, or just some. For example if you only want to use and and or gates in your design select Logic from under the Categories portion of the browser. Select the part you want to use, and then place it in your schematic by clicking where you want it to be placed.

 

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Figure 5: Symbol Browser and Sche

 

• Once the part is placed, it can then be wired using the wire tool (Figure 6) located on the tool bar at the top of your schematic window. To wire parts together, select the wire tool. Place the cursor over the part, near the port you wish to have the wire connected to. Four little red boxes should appear at the port (see Figure 7). Click to mouse button to start wiring. (Note: This is not a click and drag process. Click, then let go.) Now drag from the highlighted port to the port you wish to connect to (Figure 8). When another set of four little red boxes appear, click and you will have a wire where the connection has been made.

Some notes about wiring:

Figure 6: Wire Tool

a) You may connect a wire to a port with out connecting it to another port. Place the cursor where you want the wire to end, and double click, thus stopping the wiring process.
b) If you make a mistake and want to delete a wire click on it. The wire, and all of its branches, will be selected (there will be boxes on the ends of each segment of wire). Then press Delete.
c) You may delete only a portion of a wire instead of the wire and all of its branches. To do so first make sure the pointer icon is selected. Then under the option to Select Branches or Select Wires choose Select Wires. Then click the section of wire you want to delete. You will know that it is selected when there are boxes at either end of the wire. Now press Delete.
d) Xilinx will not allow you to draw diagonal wires. It will automatically make them square.

Figure 7: Highlighted Port

Figure 8: Wire Connection

Labeling Wires

You also have the ability to assign wires to pin numbers on the FPGA chip. The actual assignment will be done later. For simulation purposes you will want to label each wire you want to see in the simulation.

		Select the labeling tool ,which will make the Add Net Name Option appear on the left of your screen.    Type in the name you want in the Name field as shown.   Click the wire you want to label and the name will appear in small blue letters above the wire.
		Some notes on labeling:      a) You may label multiple wires with the same name. Wires with the same name are essentially wired together.    b) You may change the name of all wires labelled the same by selecting Name the branch's net instead of Name the branch, changing the name    under the Name field and then clicking any wire you want changed. Now all wires that had the previous name will be changed to the new label name.    c) You may label bus wires by selecting Increment the name instead of Keep the name. For example, if you have 4 data lines and we give the first one the name D0, the other lines will be labeled D1, D2, and D3, in the order that you click on them.

 

Simulation

To use the simulator I decided to create a small circuit that consists of only two gates:

ModelSim is used to simulate the schematics made in Xilinx. This makes it possible to simulate your design in Xilinx to verify its operation. You may do so once your circuit is constructed by the following steps:
 

1. In Project Navigator highlight the schematic you want to simulate (example fan alarm circuit).
   
    
2. Double click on Launch ModelSim Simulator from the Xilinx Project Navigator Window as seen in Figure 9.
   
    

Figure 9: Where to launch ModelSim