******************************************
                   * ASSURA 3.1 Product->FEATURE breakdown  *
                   ******************************************

ASSURA 3.1 Product: (Name [Version])
72110: (Assura(TM) Design Rule Checker [3.1])
72120: (Assura(TM) Layout Vs. Schematic Verifier [3.1])
72130: (Assura(TM) Parasitic Extractor [3.1])
72131: (Assura(TM) RCX Field Solver Option [3.1])
72132: (Assura(TM) RCX Parasitic Inductance Option [3.1])
72140: (Assura(TM) Graphical User Interface Option [3.1])
72150: (Assura(TM) Multiprocessor Option [3.1])


                    ****************************************
                    * IC 5.0.33 Product->FEATURE breakdown *
                    ****************************************

IC 5.0.33 Product: (Name [Version])
12141: (Cadence(R) Design Framework Integrator's Toolkit [5.0])
21060: (Virtuoso(R) Schematic VHDL Interface [5.0])
21400: (Virtuoso(R) Schematic Editor Verilog(R) Interface [5.0])
276: (Virtuoso(R) Schematic Editor HSPICE Interface [5.0])
3000: (Virtuoso(R)-XL Layout Editor [5.0])
305: (Virtuoso(R) Compactor [5.0])
32100: (Virtuoso(R) Analog Oasis Run-Time Option [5.0])
32120: (Virtuoso(R) Electronic Design for Manufacturability Option [5.0])
32150: (Cadence(R) SPICE [5.0])
32500: (Virtuoso(R) Spectre(R) Circuit Simulator [5.0])
32520: (Virtuoso(R) Spectre(R)-RF Simulation Option [5.0])
32760: (Virtuoso(R) Analog HSPICE Interface Option [5.0])
34500: (Virtuoso(R) Schematic Editor [5.0])
34510: (Virtuoso(R) Analog Design Environment [5.0])
365: (Dracula(R) Graphical User Interface [4.9])
570: (Virtuoso(R) Schematic Composer to design compiler integration [5.0])
681: (Cadence(R) RC Network Reducer Option [3.0])
70000: (Virtuoso(R) AMS Designer Environment [1.0])
70520: (Dracula(R) Physical Verification and Extraction Suite [4.8])
71520: (Diva(R) Physical Verification and Extraction Suite [5.0])
900: (Cadence(R) SKILL Development Environment [CAT 97B])
940: (Virtuoso(R) EDIF 200 Reader [5.0])
945: (Virtuoso(R) EDIF 200 Writer [5.0])
952: (Virtuoso(R) EDIF 300 Connectivity Reader/Writer [5.0])
953: (Virtuoso(R) EDIF 300 Schematic Reader/Writer [5.0])




                    ****************************************
                    * ICC 11.1 Product->FEATURE breakdown  *
                    ****************************************

ICC 11.1 Product: (Name [Version])
3300: (Virtuoso(R) Chip Assembly Router [11.1])




                     **************************************
                     * LDV 5.1 Product->FEATURE breakdown *
                     **************************************

LDV 5.1 Product: (Name [Version])
25010: (Cadence(R) Simulation Analysis Environment [5.1])
28000: (Cadence(R) NC-Sim Mixed-Language Simulator [5.1])
28050: (NC-Sim Desktop [5.1])
28200: (Cadence(R) NC-Verilog(R) Simulator [5.1])
28250: (Verilog(R) Desktop Simulator [5.1])
28400: (Cadence(R) NC-VHDL Simulator [5.1])
28450: (Cadence(R) VHDL Desktop Simulator [5.1])
29300: (Incisive(TM) Unified Simulator [5.1])
29370: (AMS Option to Incisive(TM) [5.1])
70001: (Virtuoso(R) AMS Designer Simulator [5.1])
V29: (FormalCheck(R) Model Checker [fcheck 3.8])




                    ****************************************
                    * PSD 15.1 Product->FEATURE breakdown  *
                    ****************************************

PSD 15.1 Product: (Name [Version])
PS1430: (Layout studio [15.1])
PS2200: (Allegro(R) AMS Simulator 210 [15.1])
PS3000: (Allegro(R) PCB Design HDL 220 [15.1])
PS3010: (Allegro(R) PCB Design CIS 220 [15.1])
PX3100: (Allegro(R) PCB SI 610 [15.1])
PX3300: (PCB mixed-signal expert [15.1])
PX3500: (Allegro(R) PCB Librarian 610 [15.1])
PX3700: (Allegro(R) PCB Design HDL 610 [15.1])
PX3710: (Allegro(R) PCB Design CIS 610 [15.1])
PX4000: (Allegro(R) Package SI 610 [15.1])



                     **************************************
                     * SOC 3.3 Product->FEATURE breakdown *
                     **************************************

SOC 3.3 Product: (Name [Version])
FE200: (Cadence(R) SoC Encounter [2002.2])
RA100: (Route Accelerator Multi-Threaded Route Option [2002.2])
SPR002: (Silicon Ensemble(TM)-PKS Optimization [1.0])



                     **************************************
                     * SPR 5.0 Product->FEATURE breakdown *
                     **************************************

SPR 5.0 Product: (Name [Version])
BGX100: (BuildGates(R) Extreme Synthesis [5.0])