| Name |
Degree |
Year |
Thesis Title |
| Anthony Slade | MSEE | 2003
| Designing, Debugging, and Deploying Configurable Computing
Machine-Based Applications Using Reconfigurable Computing Application
Frameworks |
| Timothy Wheeler | MSEE | 2001
| Improving Design Observability and Controllability For Functional
Verification of FPGA-Based CIrcuits Using Design-Level Scan
Techniques |
| Russell Frederickson | MSEE | 2001
| Constant Coefficient Multiplication |
| Jeremy Anderson | MSEE | 2000
| Module Generation for FPGAs |
| Matthew. Severson | MSEE | 2000
| Relational Placement and Layout Manipulation With JHDL for
FPGAs |
| Michael Rytting | MSEE | 2000
| Using JHDL To Visualize, Debug, and Execute External Designs
|
| Paul Graham | MSEE | 1996 |
A Description, Analysis, and Comparison of a
Hardware and a Software Implementation of the Splash Genetic Algorithm
for Optimizing Symmetric Traveling Salesman Problems |
| Gregory Thompson | MSEE | 1995 |
Memory Hierarchy Performance of Transaction Processing Workloads |
| Cameron McNairy | MSEE | 1995 |
A Linear System of Equations Solver on Splash-2 -- A Systolic
Approach |
| J. Kelly Flanagan | PhD | 1993 |
A New Methodology for Accurate Trace Collection and Its Application to Memory Hierarchy Performance Modeling |
| Paul Michelsen | MSEE | 1992 |
Optimization of the Numerically Intensive ACERC Combustion Code For
Execution on the New Super-Workstations |
| Curtis Collyer | MSEE | 1992 |
A Timing Analysis of Two-Level Cache Memory Systems |
| J. Kelly Flanagan | MSEE | 1989 |
Processor Design Using Path Programmable Logic |
| Robert Martell | MSEE | 1988 |
Systolic Array Simulator: SYSTOLE |
| Roger Pennington | MSEE | 1988 |
FPM: A Low Cost Floating Point Audio Signal Processor |
| Gary Brown | MSEE | 1986 |
A Port Reordering Algorithm to Reduce Interconnect Length and
Crossovers for Improved Routability of Integrated Circuits |
| Darryl Morrell | MSEE | 1986 |
Compaction of Constrained Tiled Circuits Using Monte Carlo
Algorithms |
| Brian Moore | MSEE | 1986 |
A Pipelined Floating-Point Systolic Array Arithmetic Processor |