This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author’s copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
Journal Publications
D. Penry, "Multicore Diversity: A Software Developer's Nightmare," ACM SIGOPS Operating Systems Review (OSR), April 2009. [abstract] (PDF, PostScript)
D. August, J. Chang, S. Girbal, D. Gracia-Perez, G. Mouchard, D. Penry, O. Temam, and N. Vachharajani, "UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development," IEEE Computer Architecture Letters, 6, August 2007. [abstract] (PDF, PostScript)
M. Vachharajani, N. Vachharajani, D. A. Penry, J. Blome, S. Malik, and D. I. August, "The Liberty Simulation Environment: A Deliberate Approach to High-Level System Modeling," ACM Transactions on Computer Systems, 24(3), August 2006, pp. 211-249. [abstract] (PDF)
M. Vachharajani, N. Vachharajani, D. A. Penry, J. Blome, and D. I. August, "The Liberty Simulation Environment, Version 1.0," Performance Evaluation Review: Special Issue on Tools for Architecture Research, 31(4), March 2004, pp. 19-24. [abstract] (PDF, PostScript)
Invited paper
Refereed Conference Publications
Z. Ruan and D. A. Penry. "Partitioning and Synthesis for Hybrid Architecture Simulators," to appear in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, May 2010.
D. A. Penry, D. Fay, D. Hodgdon, R. Wells, G. Schelle, D. I. August and D. Connors. "Exploiting Parallelism and Structure to Accelerate the Simulation of Chip Multi-processors," in Proceedings of the 12th International Symposium on High-Performance Computer Architecture, February 2006, pp. 27-38. [abstract] (PDF, PostScript)
D. A. Penry and D. I. August. "Optimizations for a Simulator Construction System Supporting Reusable Components," in Proceedings of the 40th Design Automation Conference, June 2003, pp. 926-931. [abstract] (PDF, PostScript)
M. Vachharajani, N. Vachharajani, D. A. Penry, J. A. Blome, and D. I. August. "Microarchitectural Exploration with Liberty," in Proceedings of the 35th International Symposium on Microarchitecture, November 2002, pp. 271-282. [abstract] (PDF, PostScript)
Winner of Best Student Paper award
R. Rajsuman and D. Penry. "Coverage of Bridging Faults by Random Testing in IDDQ Test Environment," in Proceedings of the 6th International Conference on VLSI Design, January 1993, pp. 136-139.
Refereed Workshop Publications
J. Chen, P. Juang, K. Ko, G. Contreras, D. A. Penry, R. Rangan, A. Stoler, L.-S. Pei, and M. Martonosi. "Hardware-Modulated Parallelism in Chip Multiprocessors," in Workshop on Design, Architecture, and Simulation of Chip Multi-Processors, November 2005. [abstract] (PDF)
D. A. Penry, M. Vachharajani, and D. I. August. "Rapid Development of a Flexible Validated Processor Model," in Proceedings of the Workshop on Modeling, Benchmarking, and Simulation, June 2005, pp. 21-30. [abstract] (PDF, PostScript)
Unrefereed Workshop/Conference Publications
Z. Ruan and D. A. Penry. "Issues in Hybrid Simulator Synthesis," in Proceedings of the 4th Workshop on Architectural Research Prototyping (WARP), June 2009. [abstract] (PDF)
Z. Ruan, K. Rehme, and D. A. Penry. "SPRI: Simulator Partitioning Research Infrastructure," in Proceedings of the 3rd Workshop on Architectural Research Prototyping (WARP), June 2008. [abstract] (PDF)
D. A. Penry. "You Can't Parallelize Just Once: Managing Manycore Diversity," position paper for the Workshop on Manycore Computing, Seattle, WA, June 2007. (PDF)
D. A. Penry, Z. Ruan, and K. Rehme, "An Infrastructure for HW/SW Partitioning and Synthesis of Architectural Simulators," in 2nd Annual Workshop on Architectural Research Prototyping, June 2007. (PDF)
Technical Reports
D. A. Penry. "The Acceleration of Structural Microarchitectural Simulation via Scheduling," PhD Thesis, Department of Computer Science, Princeton University, TR-767-06, September 2006. [abstract] (PDF, PostScript)
D. A. Penry, M. Vachharajani, and D. I. August, "Rapid Development of Flexible Validated Processor Models", Liberty Research Group Technical Report 04-03, November 2004. [abstract] (PDF, PostScript)
M. Vachharajani, N. Vachharajani, D. A. Penry, J. A. Blome, S. Malik, and D. I. August. "The Liberty Simulation Environment: A Deliberate Approach to High-Level System Modeling," Liberty Research Group Technical Report 04-02, March 2004. [abstract] (PDF, PostScript)
D. A. Penry. "IDDQ Fault Coverage by Random Testing," Master's Thesis, Department of Computer Engineering, Case Western Reserve University, April 1992.
Patents
D. A. Penry and K. B. Normoyle. "Phase enable and clock generation circuit," U.S. Patent 6,100,732, August 2000.
G. Aybay, S. Aggarwal, and D. Penry. "High speed modular internal microprocessor bus system," U.S. Patent 6,003,104, December 1999.
D. A. Penry. "Partial parity correction logic," U.S. Patent 5,944,808, August 1999.
K. Normoyle, D. Penry, and J-C. Su. "Multiple bus bridge system for maintaining a complete order by delaying servicing interrupts while posting write requests," U.S. Patent 5,894,587, April 1999.
Released Software
M. Vachharajani, D. A. Penry, N. Vachharajani, J. A. Blome, and D. I. August, "Liberty Simulation Environment Version 1.0," December 2003.
http://bardd.ee.byu.edu/Software/LSE
