1. Single Element Semiconductors

   1. Silicon, Si - the most common semiconductor, atomic number 14, energy gap Eg = 1.12 eV - indirect bandgap; crystal structure - diamond, lattice constant 0.543 nm, atomic concentration 5x1022 atoms/cm-3, index of refraction 3.42, density 2.33 g/cm3, dielectric constant 11.7, intrinsic carrier concentration 1.02 x 1010 cm-3, mobility of electrons and holes at 300 K: 1450 and 500 cm2/V-s, thermal conductivity 1.31 W/cm-oC, thermal expansion coefficient 2.6 x 10-6 1/oC, melting point 1414 oC; excellent mechanical properties (MEMS applications); single crystal Si can be processed into wafers up to 300 mm in diameter.
   2. Ge, C, Sb.

2. Silicon on Insulator (SOI)

   1. Only a thin layer on the surface of a silicon wafer is used for making electronic components; the rest serves essentially as a mechanical support. The role of SOI is to electronically insulate a fine layer of monocrystalline silicon from the rest of the silicon wafer. Integrated circuits can then be fabricated on the top layer of the SOI wafers using the same processes as would be used on plain silicon wafers. The embedded layer of insulation enables the SOI-based chips to function at significantly higher speeds while reducing electrical losses. The result is an increase in performance and a reduction in power consumption. There are two types of SOI wafers. Thin film SOI wafers have a device layer <1.5 ?m and thick film wafers have a device layer >1.5 ?m.
   2. Wafer bonding. - In this process the surface of two wafers are coated with an insulating layer (usually oxide). The insulating layers are then bonded together in a furnace creating one single wafer with a buried oxide layer (BOX) sandwiched between layers of semiconductor. The top of the wafer is then lapped and polished until a desired thickness of semiconductor above the BOX is achieved.
      
   3. SIMOX - Separation by Implantation of Oxide. In this process a bulk semiconductor wafer is bombarded with oxygen ions, crating a layer of buried oxide. The thickness of intrinsic semiconductor above the box is determined by the ion energy. An anneal reinforces Si-O bonds in the BOX.
      
   4. Smart Cut - The wafer bonding method is used to form the BOX, but instead of lapping off excess semiconductor (which is wasteful) a layer of hydrogen is implanted to a depth specifying the desired active layer of semiconductor. An anneal at ~500^oC splits the wafer along the stress plane created by the implanted hydrogen. The split wafer may then be reused to form other SIO wafers.
      

3. III-V Semiconductors

   1. Gallium Arsenide, GaAs - After silicon second the most common semiconductor, energy gap Eg = 1.43 eV, direct bandgap; crystal structure - zinc blend, lattice constant 5.65 Ang., index of refraction 3.3, density 5.32 g/cm³, dielectric constant 12.9, intrinsic carrier concentration 2.1 x 10⁶ cm^-3, mobility of electrons and holes at 300 K - 8500 and 400 cm²/V-s, thermal conductivity 0.46 W/cm-^oC, thermal expansion coefficient 6.86 x 10^{-6 o}C^-1; thermally unstable above 600 ^oC due to As evaporation; does not form sufficient quality native oxide; mechanically fragile; due to direct bandgap commonly used to fabricate light emitting devices; due to higher electron and hole mobilities, also foundation of the variety of high-speed electronic devices; bandgap can be readily engineered by forming ternary compounds based on GaAs, e.g. AlGaAs.
   2. Gallium Nitride, GaN - wide bandgap III-V semiconductor with direct bandgap 3.5 eV wide; among very few semiconductors capable of generating blue radiation, GaN is used for blue LEDs and lasers; intrinsically n-type semiconductor but can be doped p-type; GaN is formed as an epitaxial layer; Lattice mismatch remains a problem, creating a high defect density. Incorporation of Indium (In_xGa_1-xN) allows control of emission from green to violet (high and low In content respectively). GaN can also be used in UV detectors that do not respond to visible light. GaN has a Wurtzite(W) or Zinc Blend(ZB) crystal structure. Lattice constant [A] 3.189(W) 5.186(ZB); Density[g/cm³] 6.15(W) 6.15(ZB); Atomic concentration [cm^-3] 8.9 x 1022(W) 8.9 x 1022(ZB); Melting point [^oC] 2,500(W) 2,500(ZB); Thermal conduct.[W/cm ^oC] 1.3(W) 1.3(W); Thermal expansion coefficient[^oC^-1] ~1x10^-6; Dielectric constant (static) 8.9(W) 9.7(ZB); Refractive index 2.4(W) 2.3(ZB);
   3. GaP - Crystal structure zinc blend; Lattice constant [A] 5.45; Density [g/cm³] 4.14; Atomic concentration [cm^-3] 4.94 x 10²²; Melting point [^oC] 1457; Thermal conductivity [W/cm ^oC] 1.1; Thermal expansion coefficient[1/^oC] 4.65x10^-6; Dielectric constant 11.1; Refractive index 3.02; Energy gap [eV] 2.26; Type of energy gap: direct; Electron mobility [cm²/V sec] 250; Hole mobility [cm²/V sec] 150;

4. II-VI Semiconductors

   1. examples: CdSe, CdTe, CdHgTe, ZnS.

5. Other Binary Semiconductors

   1. Silicon carbide, SiC - semiconductor featuring energy gap Eg = 2.9 -3.05 eV (wide bandgap semiconductor), indirect bandgap; SiC can be obtained in several polytypes- most common hexagonal in the form of either 4H or 6H polytypes; parameters vary depending on polytype; Intrinsically n-doped; p-type doping and n-type conductivity control can be obtained by doping with aluminum and nitrogen respectively. SiC features higher than Si and GaAs electron saturation velocity; excellent semiconductor but difficult and expensive to fabricate single-crystal wafers; excellent for high power, high temperature applications; SiC is closely lattice matched to GaN, has a thermal expansion coefficient close to GaN, and is available in both conductive and semi-insulating substrates. Thus it is often used as a substrate for GaN epitaxial layers. SiC wafers 75 mm in diameter are available commercially.
      

      Crystal Structure	3C-SiC (cubic)	6H-SiC (hexagonal)
      Lattice constant [A]	4.36	3.08
      Thermal conductivity [W/cm oC]	5
      Melting point	sublimes > 2,100 oC
      Dielectric constant	9.7
      Energy gap [eV]	2.3	3.03
      Electron Drift Mobility [cm2/V sec]	800	400
      Hole Drift Mobility [cm2/V sec]	40	100

6. Ternary Semiconductors

   1. Direct Bandgap Energy calculator for ternary semiconductor alloys.

7. Quaternary Semiconductors

8. Fiber Optic

   1. Silicon is the most economical IR material available. Both P-type and N-type substrates are acceptable for IR optics provided that they offer transmission greater than 50% in the 1.5 to 6 micron wavelength. Generally speaking, for N-type, the resistivity should be greater than 20 ohm-cm and, for P-type, greater than 40 ohm-cm. For use in the near IR, this is not so critical, but for applications for the far IR, resistivity can be critical. Float Zone Silicon most always meets criteria for optical use. Under certain circumstances, CZ silicon will also be adequate.
   2. GaN - blue laser/LED
   3. GaInN - green laser/LED
   4. GaAs - red laser/LED

9. Superconducting

10. Glass

11. Fused Quartz

    1. Not to be confused with fused silica, fused quartz is naturally occurring crystalline silica (Silicon Dioxide) from stone, sand, rock or lumps in its melted form. Density (at 20º C): 2.2 g/cm³; Thermal Coefficient of Expansion: 5.5 x 10-7/°C; Strain Point: 1120°C; Refractive Index: 1.458; Dielectric Constant: 3.75.

12. Fused Silica

    1. Density (at 20º C): 2.2 g/cm³; Thermal Coefficient of Expansion: 5.5 x 10-7/°C; Strain Point: 990°C; Annealing Point: 1075°C; Softening Point: 1585°C; Refractive Index(l=589.3nm): 1.459; Dielectric Constant: 3.8.

13. Epitaxial Silicon

    1. Single crystal silicon grown on top of (usually) P+ or N+ type substrate.

14. Organic semiconductor

    1. New semiconductor material based completely on organic components (primarily carbon, hydrogen, and oxygen); these low-cost semiconductors can be formed as a thin film on any substrate. some organic semiconductors maintain their electrical properties even under strain, allowing for flexible substrates; much more resistive (~ 1014 ohm-cm) than inorganic semiconductors;

1. Crystallographic Properties of Si
2. Typical Sizes of Semiconductor Wafers
   1. The Diameter of a wafer is measured through its center and not through any flats.
   2. 1 inch or 25mm
   3. 2 inch or 50mm
   4. 3 inch or 75mm
   5. 4 inch or 100mm
   6. 5 inch or 125mm
   7. 6 inch or 150mm
   8. 8 inch or 200mm
   9. 9 inch or 300mm – newest generation of wafer sizes.
3. Doping and Resistivity
   1. A p-type wafer is usually doped with Boron, although Gallium can also be used (rare). P+ wafers are heavily doped and typically have resistances of <1 Ohm/cm². P+ wafers are often used for Epi substrates. P- wafers are lightly doped with typical resistances of >1 Ohm/cm². The most common crystal orientations for P-type wafers are {100} and {111}.
   2. N-type wafers are doped with Phosphorus, Antimony, or Arsenic. N+ wafers are heavily doped with resistances <1 Ohm/cm². N- wafers are lightly doped with resistances >1 Ohm/cm².
   3. Resistivity is very important to good electronic devices and for growing uniform thermal oxides. High resistivity silicon can only be produced using the Float Zone (FZ) crystal growth method, which does not use a crucible during crystal growth. The Czochralski (CZ) method uses a quartz crucible during crystal growth, and oxygen from the crucible unintentionally dopes the material. The oxygen dopant behaves as an n-type impurity and impedes high resistivity. Low resistivity n-type material is achieved using Arsenic doping.
   4. Wafer flats in relation to doping
4. Standards by which wafer quality is measured

   1. Cleanliness

      1. Light point defects (LPDs) - Unwanted particles on surface of wafer.
      2. Particles measured by total number found across a certain area of wafer. Some edge exclusions are applied.

   2. Flatness, Planarity

      1. total thickness variation (TTV) — Absolute difference in thickness between the thickest and thinnest parts of wafer. A typical value on a 8" wafer would be less than 15 um.
      2. Warp – The difference between minimum and maximum values of the wafer surface measured from a reference plane (usually the backside of the wafer). Deviations include both concave and convex variations. Warp is a bulk property. A good warp number on an 8" wafer is less than 20 um.
      3. Global Total Indicated Reading (GTIR) — Maximum peak to valley deviation of a wafer from a given reference plane (often the backside of the wafer).
      4. Site TIR – similar to GTIR except on smaller sites on wafer. Site TIR can be a parameter of greater importance then global TIR when resolving submicron geometries.
      5. Bow – Concavity or deformation of the wafer measured from the center independent of any thickness variation. Bow is a bulk property. Good bow on a 8" prime wafer is less than 30 um.

   3. Flatness effects on thin films

   4. Defects

      1. Defects in Silicon are one of the principle causes for rejection of Silicon wafers.
      2. There are many defects associated with Silicon wafers. Most are caught at the Silicon Manufacturer, but some are not. Some so called "Prime wafers" not purchased from manufacturers may be rejects.
      3. Wafer defects range from pits and micro-scratches in the Silicon surface to imperfections buried in the Silicon bulk. Crystalline defects which are introduced into the crystals during the crystal growth are point defects, dislocations, stacking faults, twins, inclusions, precipitates, and microdefects.
      4. Point defects - include vacancies, interstitials, antisite defects, foreign atoms. Melt stoichiometry controls the concentration of point defects (and electrical properties of material).
      5. Dislocations - Originate during bulk crystal growth from three mechanisms:
         
         Nonuniform heat flow during solidification resulting in thermal stress.
         condensation of excess point defects forming dislocation loops.
         Propagation of dislocations from defective seed crystal or punching out of dislocations from foreign particles or inclusions.
         Parameters affecting dislocation density:
         
         seed quality and necking
         cone angle
         ambient pressure
         melt stoichiometry
         crystal diameter
      6. Stacking faults and twins - two dimensional defects observed frequently in III-V semiconductor crystals. A stacking flaw is a flaw in the stacking sequence of atomic planes in the crystal lattice. A twin represents two regions in the crystal with one region a mirror reflection of the other across a lattice plane (twin plane) that is common to both regions. Twinning can occur as a result from:
         
         nucleation at the crucible wall
         >deviation from melt stoichiometry
         excessive thermal stresses due to variations in crystal diameter
         instabilities in the shape of the crystal growth front
         thermal decomposition following growth
         excessive facet formation
      7. Line defects
      8. plane defects
      9. volume defects
5. Grades
   1. Prime wafers - "Prime" refers to the highest possible grade of a silicon wafer, however there are a variety of "prime" wafers. SEMI indicates the bulk, surface, and physical properties required to label silicon wafers as true “Prime Wafers,” however wafers meeting these specs are rare and quite expensive. A true prime wafer is a device quality wafer that any major fab could use for the latest technology semiconductor devices. A true prime wafer will be very smooth, site inspected for flatness meeting a spec of at least .3um on a 20mm x 20mm site and defect free.
   2. Test wafers - A silicon wafer used in process monitoring or other testing. Bulk, surface and physical properties are less stringent than required for prime wafers. Test wafers are often wafers failed one or more specifications in the attempt to make prime wafers. Test wafers have no flatness spec, no backside specs, and a very wide resistivity range. Unless a process is highly sensitive to uniformity, test wafers generally perform well.
   3. Reclaim wafers - A wafer that has been used in a semiconductor manufacturing process after which the surface is refinished (repolished) to a test grade quality. As larger diameter silicon wafers were being developed, the cost of these wafers increased. In order to provide savings to customers, the wafer reclaim process was developed. Reclaimed wafers are stripped of films, metals or other contaminants, cleaned and then polished to specification. This allows three and four uses out of one wafer as the waver is thinned with each re-polish. Typically reclaimed wafers are sold without tight restrictions on resistivity.
   4. Recycled wafers - A wafer that has been cleaned to a degree suitable for reprocessing. Only certain surface treatments can be chemically removed without damaging the silicon substrate.
   5. Epi wafers – have a thin layer of N- silicon grown on the surface of a P+ (Boron) wafer providing a very flat surface suitable for submicron lithography. Epi wafers are a less expensive alternative to high priced Prime wafers discussed above. Silicon atoms are deposited on a bare silicon wafer in a CVD reactor. When the chemical reactants are controlled and the system parameters are set correctly, the depositing atoms arrive at the wafer surface with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the wafer atoms. Thus an epitaxial film deposited on a <111>-oriented wafer will take on a <111> orientation. If a dielectric or other film is already present on the wafer, the epi layer will be polysilicon. Epi wafers will always have a characteristic oxide backseal on them (usually 3-5,000Å). This oxide is placed on the backside of the wafer to prevent Boron from outgassing and contaminating the n-doped front side during the high temperature deposition of the epi-layer.
   6. Furnace Grade - Furnace grade wafers have very tightly controlled electrical characteristics. Typically they are used for high temperature applications or thin film depositions. Furnace grade wafers display very tightly controlled Oxygen content, resistivity, radial resistivity gradient (RRG) and carbon content. The wafers are also doped very evenly. All of these factors help films grow uniformly without slip lines or stress fractures.
   7. Coin-roll wafers – Wafers that fail spec for any reason at all different steps of the Silicon wafer manufacturing process are collected and sold as coin-roll wafers. Thus some of the wafers are unpolished or scratched and they have different resistivities and crystal orientations. Silicon vendors buy these wafers in large containers with hundreds of wafers stacked on top of each other inside, resembling a roll of coins. These wafers are sorted for type and resistivity and recycled into test wafers.
   8. Particle wafers - Particle grade wafers typically refer to 300 mm wafers and have a minimal amount of contaminants, or particles. Particles are measured at various sizes, 0.09 um, 0.12 um, 0.16 um. 0.20 and 0.30 are common specifications. The number of particles at a certain size is limited to a predetermined number, 10, 20, 50, etc. The specification is written: <50@>0.12 um. This means there are less than or equal to 50 particles greater than 0.12 um in size on the entire wafer.
   9. Mechanical grade wafers -- .... Although the specifications can be applied to any diameter wafer, the term “mechanical grade” most often refers to a 300 mm specification.
6. Backside Treatment
   1. Wafers typically etched (acid = smooth quasimirror; caustic = dull finish)
   2. Gettering – wafers receive a backside coating of Polysilicon. In subsequent process steps, this backside treatment will draw defects in the Silicon towards the backside of the wafer and away from the front side where the devices are being built.
   3. Double polished
7. SEMI Standards
   1. Wafers conforming to SEMI Standards will have the characteristics listed below:
   2. Diameter of wafer: 50 mm (2")
      1. Primary flat on (01 T) plane ± 0.5°.
      2. Secondary flat 90° ± 1° ccw to primary flat.
      3. Primary flat length: 15.9 ± 1.5 mm.
      4. Secondary flat length: 8.0 ± 1.5 mm.
   3. Diameter of wafer: 75 mm (3")
      1. Primary flat on (01 T) plane ± 0.5°.
      2. Secondary flat 90° ± 1° ccw to primary flat.
      3. Primary flat length: 22.2 ± 2.0 mm.
      4. Secondary flat length: 11.2 ± 1.5 mm.
   4. Diameter of wafer: 100 mm (4")

      1. Thickness:	525 um (20.5 mils)
         Primary flat length:	32.5 mm
         Secondary flat length:	18.0 mm
         Bow, max:	40 um
         Warp, max:	40 um
         TTV (flatness), max:	10 um
         Primary flat orientation:	<110>

   5. Diameter of wafer: 150 mm (6")

      1. Thickness:	675 um (26.3 mils)
         Primary flat length:	57.5 mm
         Secondary flat length:	37.5 mm
         Bow, max:	60 um
         Warp, max:	60 um
         TTV (flatness), max:	10 um
         Primary flat orientation:	<110>

      Glossary of common wafer related terms